UVM Advanced

This 4-days course designed for advanced ASIC & FPGA verification engineers that would like to enhance their UVM skills to verify complex digital designs more efficiently.
The training is loaded with extensive practical hands-on labs to verify that the theory is understood plus introduce more use cases than covered in theory slides.

The first day introduces the self-checking testbench approach and how to create a scoreboard, then virtual sequences and virtual sequencers concept is introduced in details for complex use cases.

The second day teaches how to create a complex stimuli generation with various advanced techniques.
Master-slave protocol is covered in details.

The third day starts with introduction of the advanced synchronization using the callback class, along with barrier synchronization, and the uvm_event class.
The day continuous by covering the end-of-test mechanism, how to raise and drop objections, how to debug UVM objections and how to set TB drain time.

The fourth day covers the connection reusability between DUT and top TB including BFM, port coerction, how to extract RTL parameters vs using package, the bind construct, UVM harness, and races between TB and DUT.
The training ends by covering how to handle exceptional situation such as reset, error injection and the uvm_heartbeat.